1. Technical Field
The present application relates to processes for forming integrated circuit devices and, more particularly, to processes for forming integrated circuit devices having a gate structure.
2. Related Art
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are have been implemented. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The creation of small features with close spacing between adjacent features can be accomplished through the use of high-resolution photolithographic processes. In general, lithography refers to processes for transferring patterns between various media. It includes techniques used for the fabrication of integrated circuits in which a silicon wafer is coated with a radiation-sensitive film (referred to as a resist layer) and then exposing selected areas of the coated surface to a light source (for example optical light, x-rays, or an electron beam) that illuminates the coated surface through an intervening master template (referred to as a mask) for a desired pattern. The lithographic coating is generally a radiation-sensitive coating that is suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The projected image may be either a negative or a positive of the subject pattern. Two basic types of photoresist have been developed over the years: positive photoresist and negative photoresist. With positive photoresist, the portion thereof that is exposed to light is removed during developing, while with negative photoresist, the portion thereof that is not exposed to light is removed. Historically, negative resists have been unsuitable for applications requiring line and space dimensions of the resist pattern which are less than 3 μm. Thus, positive resists have supplanted negative resists for very large scale integration (VLSI) devices.
One particular problem related to the use of positive resist can be fatal to integrated circuits. Raised features often acquire unwanted re-entrant profiles during processing. Several known mechanisms will produce re-entrant profiles on multi-layer features. One common mechanism often manifests itself during an etch of sequentially deposited layers. If one or more underlying layers etch at a faster rate than the top-most layer, a recessed or re-entrant profile will result. Another common mechanism involves chemical vapor deposition (CVD). For certain CVD reactions, as material deposits on a rectangular, raised feature, the deposition rate tends to be greater at the corners, resulting in a feature having a re-entrant profile. Another mechanism that results in re-entrant profiles on multi-layer features is related to oxidation effects. For example, if the sidewall of a multi-layer stack containing a tungsten silicide layer in all but the base layer is oxidized, the edges of the tungsten silicide layer will oxidize much more rapidly than the other layers, resulting in a re-entrant sidewall profile. There are also several mechanisms, such as mask proximity effects, and etch effects, that are known to cause re-entrant profiles on single layer features. The differential etch rate that results from a doping gradient in a single layer is a well-known example of the latter phenomenon. Generally speaking, the greater the dopant level, the faster the etch rate.
If a raised feature has a re-entrant profile, any positive resist that is beneath the overhang created by the re-entrant profile cannot be exposed during the printing (exposure) process. Thus, the resist beneath the overhang will remain in place after developing. This is particularly problematic when a conductive layer that has been deposited over dielectrically-coated, re-entrant profile features must be selectively etched to form multiple portions of the conductive layer that must be detached and electrically decoupled from one another. The re-entrant profile may provide a path which shorts together several of the multiple portions of the conductive layer that should be electrically isolated from one another. Such problems make it difficult to maintain a desirable critical dimension, particularly for 65 nm and smaller technology design nodes.
Thus, it is desirable to find alternative approaches for the manufacturing of integrated circuits in order to allow for desired critical dimensions without significant increases in manufacturing process complexity and costs.